The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing a strain relaxed silicon germanium layer that has a low defect density, and a method of forming the same.
Graded buffer layers (GBLs), also referred to as strain relaxed buffer layers, are currently one of the front up approaches for 7 nm node and beyond technologies. GBLs can enable dual channel material FinFETs on a same substrate. For example, and after the relaxed top silicon germanium layer (SiGe) of the GBL is formed, strained silicon can be formed on a first portion of the relaxed top SiGe layer and in an nFET device region, and a high germanium percentage SiGe alloy can be formed on a second portion of the relaxed top SiGe layer and in a pFET device region. The biggest challenge with the process and device yields is the defect density at the surface of the GBL.
It has been shown that the thicker the SiGe layer of the GBL is, the lower the defect density at the surface of the SiGe layer is. The reason for that is the movement and subsequent annihilation of the threading dislocations in the SiGe layer become easier as the thickness of the SiGe layer increases. As thicker SiGe layers are grown, a large bow of the silicon wafer is observed. The relaxed SiGe layer is at a larger lattice constant than the silicon substrate and as the thickness of the SiGe layer increases, the more the underlying silicon wafer gets bowed. Five micrometer to eight micrometer thick SiGe layers can be grown safely, but for slightly thicker SiGe layers (10 micrometers to 12 micrometers), there is the possibility of wafer breakage. As such, and for a SiGe layer thickness range needed to have desired low defect densities (less than 100 defect atoms/cm2), wafer breakage will occur due to the large bow stress applied to the wafer. Additional acceptable bow (no wafer breakage) will create problems with semiconductor tool processing. Examples include wafer robot handling issues or non-uniformity of processes due to the bowed wafer. As such, there is a need to provide a method to form a GBL having a SiGe layer in which defect density is low and bowing issue is mitigated.